The integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) is improved by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area and/or lower height than packages of the past, in some applications. Thus, new packaging technologies, such as a three dimensional (3D) packaging arrangement, have been developed. A 3D packaging arrangement has a central processing chip and each active circuit block located on a separate plane. Electrical routing lines are formed which connect active circuit blocks located on one plane with active elements on another plane.